The present invention relates to a semiconductor integrated circuit device, a method of testing a semiconductor integrated circuit device and a method of manufacturing a semiconductor integrated circuit device. More particularly, the present invention concerns an effective technique for use in a technique for determining a write failure and a precharge failure in a high-speed operating dynamic random access memory (RAM) configured as a semiconductor integrated circuit device, by using a low-speed testing apparatus, for example.
A dynamic RAM configured as a semiconductor integrated circuit device is tested by application of an appropriate operation control signal and a data signal and by reference to output data. In cases where it is necessary to confirm the operating speed of the dynamic RAM and where it is necessary to confirm an operation timing margin, testing is performed after periods of synchronization signals which are called a row address strobe (RAS) signal and a column address strobe (CAS) signal are appropriately set for testing. Namely, a period operation required for operation for selecting/nonselecting word lines in the RAM, amplifying operation of sense amplifiers, and precharging operation of bit lines, and the like vary according to variations in the fabrication of the RAM. Testing as to whether or not the variations of the period required for various appropriate operation fall within an allowable range becomes possible by the appropriately setting the synchronization signals.
Development of semiconductor integrated circuit device technologies in recent years has been remarkable, and increasingly highly sophisticated functions and higher-speed operation have been made possible. As for the dynamic RAMs as well, which are configured as semiconductor integrated circuit devices, those operating at a high speed at a frequency in the neighborhood of 100 MHz or below have become necessary and have been made available. Testing apparatus or testers which can be realistically used for practical purposes for the dynamic RAMs capable of high-speed operation of that kind operate at relatively low speeds with the clock operation of about 30 MHz.